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  silego technology, inc. rev 1.03 000-0046170-103 revised october 10, 2017 greenpak programmable mixed-signal matrix slg46170 block diagram features ? logic & mixed signal circuits ? highly versatile macrocells ? read back protection (read lock) ? 1.8v (5%) to 5v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? 14-pin stqfn: 2 x 2.2 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gnd gpio gpio gpio gpio 2 3 49 10 11 gpi vdd 1 14-pin stqfn (top view) gpio gpio 8 67 14 13 gpio gpio gpio gpio gpio 5 12 pin4 gpio programmable delay rc oscillator pin 5 gpio pin 1 vdd pin 2 gpi pin 3 gpio pin 14 gpio pin 13 gpio filter_0 filter_1 additional logic functions look up tables (luts) counters/delay generators cnt0 cnt1 2-bit lut2_1 3-bit lut3_3 2-bit lut2_2 3-bit lut3_0 3-bit lut3_2 3-bit lut3_1 3-bit lut3_5 3-bit lut3_7 3-bit lut3_6 combination function macrocells 2-bit lut2_0 or dff4 3-bit lut3_8 or pipe delay cnt2 cnt3 cnt4 cnt5 cnt6 cnt7 d flip flops (dff) / latches dff0 dff1 dff2 dff3 dff5 dff6 2-bit lut2_5 2-bit lut2_4 3-bit lut3_4 3-bit lut3_3 4-bit lut4_0 3-bit lut3_9 pin 6 gpio pin 7 gpio pin 9 gnd pin 8 gpio pin 12 gpio pin 11 gpio pin 10 gpio
000-0046170-103 page 1 of 86 slg46170 1.0 overview the slg46170 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macrocells of the slg46170. this highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single in tegrated circuit. the macrocells in the device include the following: ? fifteen combinatorial look up tables (luts) ? five 2-bit luts ? nine 3-bit luts ? one 4-bit lut ? two combination function macrocells ? one selectable ff/latch or 2-bit lut ? one selectable pipe delay or 3-bit lut ? pipe delay C 16 stage / 3 output ? eight counter / delay generators (cnt/dly) ? one 14-bit delay/counter ? one 14-bit delay/counter wi th external clock/reset ? four 8-bit delays/counters ? two 8-bit delays/counters with external clock/reset ? six d flip-flop / latches (dff) ? pipe delay C 16 sta ge/3 output (part of c ombination function m acrocell) ? programmable delay ? additional logic functions C 2 deglitch filters ? rc oscillator (rc osc)
000-0046170-103 page 2 of 86 slg46170 2.0 pin description 2.1 functional and pro gramming pin description pin # pin name function programming function 1 vdd power supply power supply 2 gpi general purpose input v pp (programming voltage) 3 gpio general purpose i/o n/a 4 gpio general purpose i/o n/a 5 gpio general purpose i/o n/a 6 gpio general purpose i/o n/a 7 gpio general purpose i/o n/a 8 gpio general purpose i/o n/a 9 gnd ground ground 10 gpio general purpose i/ o programming mode control 11 gpio general purpose i/o programming id pin 12 gpio general purpose i/o programming sdio pin 13 gpio general purpose i/o programming srdwb pin 14 gpio general purpose i/o or external clock programming scl pin
000-0046170-103 page 3 of 86 slg46170 3.0 user programmability non-volatile memory (nvm) is used to configure the slg46170s c onnection matrix routing and macrocells. the nvm is one-time-programmable (otp). how ever, silegos greenpak develop ment tools can be used to configure the connection matrix and macrocells, without programming the nvm, to allow on-chip e mulation. this configuration will remain active on the device a s long as it remains powered and c an be re-written as needed to f acilitate rapid design changes. when a design is ready for in-circuit testing, the same greenpa k development tools can be used to program the nvm and create samples for small quantity builds. once the nvm is programmed, the device will retain this conf iguration for the duration of i ts lifetime. once the design is finalized, the design file c an be forwarded to silego to integ rate into the produ ction process. figure 1. steps to create a cu stom silego greenpak device product definition customer creates their own design in greenpak designer program engineering samples with greenpak development tools customer verifies greenpak in system design e-mail design file to greenpak@silego.com e-mail product idea, definition, drawing, or schematic to greenpak@silego.com silego applications engineers will review design specifications with customer samples and design & characterization report sent to customer customer verifies greenpak design custom greenpak part enters production greenpak design approved in system test greenpak design approved greenpak design approved emulate design to verify behavior
000-0046170-103 page 4 of 86 slg46170 4.0 ordering information part number type SLG46170V 14-pin stqfn SLG46170Vtr 14-pin stqfn - tape and reel (3k units)
000-0046170-103 page 5 of 86 slg46170 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical charac teristics (1.8 v 5% v dd ) parameter min. max. unit supply voltage on vdd relative to gnd -0.5 7 v dc input voltage g nd - 0.5 vdd + 0.5 v maximum average or dc current (through pin) push-pull 1x -- 8 ma push-pull 2x -- 10 od 1x -- 8 od 2x -- 12 od 4x -- 25 current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 1300 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 1.80 1.89 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v ih high-level input voltage logic input 1.100 -- -- v logic input with schm itt trigger 1.270 -- -- v low-level logic input 0.980 -- -- v v il low-level input voltage logic input -- -- 0.690 v logic input with schm itt trigger -- -- 0.440 v low-level logic input -- -- 0.520 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull 1x, open drain pmos 1x, i oh = 100 ? a 1.690 1.789 -- v push-pull 2x, open drain pmos 2x, i oh = 100 ? a 1.700 1.794 -- v v ol low-level output voltage push-pull 1x, i ol = 100 ? a -- 0.008 0.030 v push-pull 2x, i ol = 100 ? a -- 0.004 0.010 v open drain nmos 1x, i ol = 100 ? a -- 0.005 0.020 v open drain nmos 2x, i ol = 100 ? a -- 0.003 0.010 v open drain nmos 4x, i ol = 100 ? a -- 0.003 0.004 v
000-0046170-103 page 6 of 86 slg46170 i oh high-level output current (see note 1) push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2 1.066 1.703 -- ma push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2 2.216 3.406 -- ma i ol low-level output current (see note 1) push-pull 1x, v ol = 0.15 v 0.917 1.689 -- ma push-pull 2x, v ol = 0.15 v 1.834 3.378 -- ma open drain nmos 1x, v ol = 0.15 v 1.375 2.534 -- ma open drain nmos 2x, v ol = 0.15 v 2.750 5.068 -- ma open drain nmos 4x drive, v ol = 0.15 v 5.500 10.136 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 84 ma t j = 110c -- -- 40 ma t su startup time from vdd rising past 1.35 v -- 0.3 -- ms pon thr power on threshold v dd level required to start up the chip 1.096 1.353 1.528 v poff thr power off threshold v dd level required to switch off the chip 0.759 0.933 1.125 v note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11 , 12, 13 and 14 to another. symbol parameter condition/note min. typ. max. unit
000-0046170-103 page 7 of 86 slg46170 5.3 electrical charac teristics (3.3v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v ih high-level input voltage logic input 1.780 -- -- v logic input with schm itt trigger 2.130 -- -- v low-level logic input 1.130 -- -- v v il low-level input voltage logic input -- -- 1.210 v logic input with schm itt trigger -- -- 0.950 v low-level logic input -- -- 0.690 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull 1x,open drain pmos 1x, i oh = 3 ma 2.735 3.120 -- v push-pull 2x, open drain pmos 2x, i oh = 3 ma 2.870 3.210 -- v v ol low-level output voltage push-pull 1x, i ol = 3 ma -- 0.130 0.228 v push-pull 2x, i ol = 3 ma -- 0.060 0.108 v open drain nmos 1x, i ol = 3 ma -- 0.080 0.147 v open drain nmos 2x, i ol = 3 ma -- 0.040 0.080 v open drain nmos 4x, i ol = 3 ma -- 0.027 0.034 v i oh high-level output current (see note 1) push-pull 1x, open drain pmos 1x, v oh = 2.4 v 6.045 12.080 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v 11.522 24.160 -- ma i ol low-level output current (see note 1) push-pull 1x, v ol = 0.4 v 4.875 8.244 -- ma push-pull 2x, v ol = 0.4 v 9.750 16.488 -- ma open drain nmos 1x, v ol = 0.4 v 7.313 12.370 -- ma open drain nmos 2x, v ol = 0.4 v 14.541 24.740 -- ma open drain nmos 4x drive, v ol = 0.4 v 25.801 49.480 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 84 ma t j = 110c -- -- 40 ma t su startup time from vdd rising past 1.35 v -- 0.3 -- ms
000-0046170-103 page 8 of 86 slg46170 pon thr power on threshold v dd level required to start up the chip 1.096 1.353 1.528 v poff thr power off threshold v dd level required to switch off the chip 0.759 0.933 1.125 v note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11 , 12, 13 and 14 to another. symbol parameter condition/note min. typ. max. unit
000-0046170-103 page 9 of 86 slg46170 5.4 electrical charac teristics (5 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v ih high-level input voltage logic input 2.640 -- -- v logic input with schm itt trigger 3.160 -- -- v low-level logic input 1.230 -- -- v v il low-level input voltage logic input -- -- 1.840 v logic input with schm itt trigger -- -- 1.510 v low-level logic input -- -- 0.780 v i lgk input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull 1x,open drain pmos 1x, i oh = 5 ma 4.190 4.780 -- v push-pull 2x, open drain pmos 2x, i oh = 5 ma 4.320 4.890 -- v v ol low-level output voltage push-pull 1x, i ol = 5 ma -- 0.157 0.270 v push-pull 2x, i ol = 5 ma -- 0.076 0.130 v open drain nmos 1x, i ol = 5 ma -- 0.102 0.180 v open drain nmos 2x, i ol = 5 ma -- 0.051 0.110 v open drain nmos 4x, i ol = 5 ma -- 0.035 0.045 v i oh high-level output current (see note 1) push-pull 1x, open drain pmos 1x, v oh = 2.4 v 22.080 34.040 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v 41.690 68.080 -- ma i ol low-level output current (see note 1) push-pull 1x, v ol = 0.4 v 7.215 11.580 -- ma push-pull 2x, v ol = 0.4 v 13.831 23.160 -- ma open drain nmos 1x, v ol = 0.4 v 10.820 17.380 -- ma open drain nmos 2x, v ol = 0.4 v 17.343 34.760 -- ma open drain nmos 4x drive, v ol = 0.4 v 30.964 69.520 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 84 ma t j = 110c -- -- 40 ma t su startup time from vdd rising past 1.35 v -- 0.3 -- ms
000-0046170-103 page 10 of 86 slg46170 pon thr power on threshold v dd level required to start up the chip 1.096 1.353 1.528 v poff thr power off threshold v dd level required to switch off the chip 0.759 0.933 1.125 v note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11 , 12, 13 and 14 to another. symbol parameter condition/note min. typ. max. unit
000-0046170-103 page 11 of 86 slg46170 5.5 idd estimator 5.6 timing estimator 5.7 typical counter/de lay offset measurements table 1. typical current est imated for each macrocell. symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit i current chip quiescent 0.5 0.8 1.0 ? a osc 25 khz, predivide = 1 3.2 5.1 7.3 ? a osc 25 khz, predivide = 8 3.0 4.4 6.0 ? a osc 2 mhz, predivi de = 1 38.5 78.2 136.2 ? a osc 2 mhz, predivi de = 8 18.3 25.7 35.5 ? a table 2. typical delay estimated for each macrocell. symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit rising falling rising falling rising falling tpd delay digital input to pp 1x 42 45 17 19 12 13 ns tpd delay digital input with schmitt trigger to pp 1x 42 43 16 17 18 12 ns tpd delay low voltage digital input to pp 1x 45 428 17 177 12 120 ns tpd delay digital input to pmos 42 - 17 - 12 - ns tpd delay digital input to nmos - 80 - 27 - 18 ns tpd delay output enable from pin, oe hi-z to 1 53 - 21 - 15 - ns tpd delay output enable from pin, oe hi-z to 0 50 - 20 - 14 - ns tpd delay lut2bit(latch) 34 33 14 13 10 9 ns tpd delay latch(lut2bit) 30 34 14 13 10 9 ns tpd delay lut3bit(latch) 38 37 18 15 13 10 ns tpd delay latch+nreset(lut3bit) 45 42 21 17 15 12 ns tpd delay lut4bit 28 33 14 13 10 9 ns tpd delay lut2bt 19 26 10 10 7 7 ns tpd delay lut3bit 28 34 14 13 10 9 ns tpd delay cnt/dly 40 38 18 15 13 11 ns tpd delay p_dly1c 380 377 166 163 123 120 ns tpd delay p_dly2c 720 718 314 312 233 231 ns tpd delay p_dly3c 1061 1060 462 460 343 341 ns tpd delay p_dly4c 1396 1400 609 609 451 451 ns tpd delay filter 200 200 78 78 53 53 ns tpd delay acmp (5mv across inputs) 3000 3000 2000 2000 2000 2000 ns tw width i/o with 1x push pull (min transmitted) 20 20 20 20 20 20 ns tw width filter (min transmitted) 150 150 55 55 35 35 ns table 3. typical counter/de lay offset measurements. parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit offset 25khz auto 19 14 12 ? s offset 2mhz auto 7 4 4 ? s frequency settling time 25khz auto 19 14 12 ? s
000-0046170-103 page 12 of 86 slg46170 frequency settling time 2mhz auto 14 14 14 ? s variable (clk period) 25khz forced 0-40 0-40 0-40 ? s variable (clk period) 2mhz forced 0-0.5 0-0.5 0-0.5 ? s tpd (non-delayed edge) 25khz/2mhz either 35 14 10 ns table 3. typical counter/de lay offset measurements. parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit
000-0046170-103 page 13 of 86 slg46170 5.8 expected delays and widths 5.9 typical pulse width performance table 4. expected delays and wid ths for programmable delay (typi cal). symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit time1 width, 1 cell mode:(any)edge detect, edge detect output 325 1 50 110 ns time1 width, 2 cell mode:(any)edge detect, edge detect output 740 3 00 225 ns time1 width, 3 cell mode:(any)edge detect, edge detect output 1020 450 340 ns time1 width, 4 cell mode:(any)edge detect, edge detect output 1350 600 450 ns time2 delay, 1 cell mode:(any)edge detect, edge detect output 44 18 14 ns time2 delay, 2 cell mode:(any)edge detect, edge detect output 44 18 14 ns time2 delay, 3 cell mode:(any)edge detect, edge detect output 44 18 14 ns time2 delay, 4 cell mode:(any)edge detect, edge detect output 44 18 14 ns time1 width, 1 cell mode: delayed (any)edge detect, delayed edge detect output 340 150 110 ns time1 width, 2 cell mode: delayed (any)edge detect, delayed edge detect output 670 300 220 ns time1 width, 3 cell mode: delayed (any)edge detect, delayed edge detect output 1000 450 335 ns time1 width, 4 cell mode: delayed (any)edge detect, delayed edge detect output 1340 600 450 ns time2 delay, 1 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 delay, 2 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 delay, 3 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 delay, 4 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 delay, 1 cell m ode: both edge delay, edg e detect output 382 375 126 ns time2 delay, 2 cell m ode: both edge delay, edg e detect output 713 169 237 ns time2 delay, 3 cell m ode: both edge delay, edg e detect output 104 5 318 350 ns time2 delay, 4 cell m ode: both edge delay, edg e detect output 137 0 466 460 ns time2 delay, 1 cell mode: both edge delay, delayed edge detect output 900 613 250 ns time2 delay, 2 cell mode: both edge delay, delayed edge detect output 1250 520 360 ns time2 delay, 3 cell mode: both edge delay, delayed edge detect output 1600 680 480 ns time2 delay, 4 cell mode: both edge delay, delayed edge detect output 1900 815 600 ns table 5. typical pulse width performance. parameter v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit filtered pulse width for filter 0 and filter 1 < 150 < 55 < 35 ns
000-0046170-103 page 14 of 86 slg46170 5.10 osc specifications table 6. 25 khz rc osc freq uency limits at t = 25 c power supply range (vdd) v minimum value, khz maximum value, khz 1.8 v 5% 24.069 25.960 3.3 v 10% 24.397 25.620 5 v 10% 24.048 25.962 2.5 v ... 4.5 v 24.214 25.868 1.71 v 5.5 v 23.703 27.515 table 7. 25 khz rc osc frequency error (error calcu lated relativ e to nominal value) at t = 25 c power supply range (vdd) v error (% at minimum) error (% at maximum) 1.8 v 5% -3.73% 3.84% 3.3 v 10% -2.41% 2.48% 5 v 10% -3.81% 3.85% 2.5 v ... 4.5 v -3.14% 3.47% 1.71 v 5.5 v -5.19% 10.06%
000-0046170-103 page 15 of 86 slg46170 5.10.1 2 mhz rc oscillator 5.10.2 osc power on delay table 8. 2 mhz rc os c frequency limits at t = 25 c power supply range (vdd) v minimum value, mhz maximum value, mhz 1.8 v 5% 1.855 2.133 3.3 v 10% 1.911 2.089 5 v 10% 1.873 2.130 2.5 v ... 4.5 v 1.894 2.110 1.71 v 5.5 v 1.760 2.164 table 9. 2 mhz rc osc frequency error (erro r calculated relative to nominal value) at t = 25 c power supply range (vdd) v error (% at minimum) error (% at maximum) 1.8 v 5% -7.25% 6.67% 3.3 v 10% -4.44% 4.43% 5 v 10% -6.33% 6.50% 2.5 v ... 4.5 v -5.28% 5.52% 1.71 v 5.5 v -12.00% 8.19% table 10. oscillators power on de lay at t=(-40..+ 85) c, dly/cnt counter data = 100; rc o sc power setting: "auto power on" power supply range (vdd) v rc osc 2 mhz rc osc 25 khz typical value, s maximum value, s typical value, s maximum value, s 1.71 8.80 12.78 19.34 24.22 1.80 8.26 12.07 18.80 24.37 1.89 7.76 11.47 18.28 23.99 2.50 5.76 8.57 15.45 19.91 2.70 5.42 7.86 14.64 18.85 3.00 5.10 7.24 13.58 17.80 3.30 4.90 7.14 12.52 16.96 3.60 4.79 7.22 11.36 16.20 4.20 4.69 7.33 9.58 12.69 4.50 4.66 7.22 8.83 11.51 5.00 4.60 7.12 7.69 9.79 5.50 4.54 7.00 6.75 8.45
000-0046170-103 page 16 of 86 slg46170 6.0 summary of macrocell function 6.1 i/o pins ? digital input (low voltage or normal voltage, with or without schmitt trigger) ? open drain outputs ? push pull outputs ? 10 k ? /100 k ? /1 m ?? pull-up/pull-down resistors ? 40 ma open drain 4x drive output 6.2 connection matrix ? digital matrix for circuit co nnections based on user design 6.3 combinational logic look up tables (luts C 15 total) ? five 2-bit lookup tables ? nine 3-bit lookup tables ? one 4-bit lookup tables 6.4 combination functi on macrocell (2 total) ? one selectable ff/latch or 2-bit lut ? one selectable pipe delay or 3-bit lut 6.5 delays/counters (8 total) ? two 14-bit delay/counter s: range 1-16384 clock cycles ? four 8-bit delays/counters : range 1-255 clock cycles ? two 8-bit delays/coun ters with external clock/reset: range 1-2 55 clock cycles 6.6 digital storage elements (6 total) ? six d flip-flops or latches 6.7 pipe delay (part of combination function macrocell) ? 16 stage / 3 output ? one 1 stage fixed output ? two 1-16 stage se lectable outputs. 6.8 programmable delay ? 150 ns/300 ns/450 ns /600 ns @ 3.3 v ? includes edge detection function 6.9 additional logic functions (2 total) ? two deglitch filter macrocells 6.10 rc oscillator ? 25 khz and 2 mhz s electable frequency ? first stage divider (4): osc /1, osc/2, osc/4, and osc/8 ? second stage divider (5): osc/1, osc/4, selectable (osc/8, osc /12, osc/24, or osc/64), osc/3, and additional osc/3 (from selectable output)
000-0046170-103 page 17 of 86 slg46170 7.0 i/o pins the slg46170 has a total of 12 mu lti-function i/o pins which ca n function as either a user defined input or output, as well as serving as a special function (s uch as outputting the voltage r eference), or serving as a signal for programming of the on-chi p non volatile memory (nvm). normal mode pin definitions are as follows: ? pin 2: general purpose input ? pin 3: general purpo se input or output ? pin 4: general purpo se input or output ? pin 5: general purpo se input or output ? pin 6: general purpo se input or output ? pin 7: general purpo se input or output ? pin 8: general purpo se input or output ? pin 10: general purpose input or output ? pin 11: general purpose input or output ? pin 12: general purpose input or output ? pin 13: general purpose input or output ? pin 14: general purpose input or output or external clock programming mode pin definitions are as follows; ? pin 1: vdd power supply ? pin 2: vpp programming voltage ? pin 9: ground ? pin 10: programming mode control ? pin 11: progr amming id pin ? pin 12: programming sdio pin ? pin 13: programming srdwb pin ? pin 14: programming scl pin of the 12 user defined i/o pins on the slg46170, all but one of the pins (pin 2) can serve as both digital input and digital o utput. pin 2 can only serve as a digital input pin. 7.1 input modes each i/o pin can be configured as a digital input pin with/with out buffered schmitt trigger, or can also be configured as a lo w voltage digital input. 7.2 output modes pins 3, 4, 5, 6, 7, 8, 10, 11, 1 2, 13 and 14 can all be configu red as digital output pins. 7.3 pull up/down resistors all i/o pins have the option for user selectable resistors conn ected to the input structure. th e selectable values on these re sistors are 10 k ? , 100 k ? and 1 m ? . in the case of pin 2, the resistors are fixed to a pull-down configuration. in the case of all other i/o pins, the internal resistors can be configured as either pull-u p or pull-downs.
000-0046170-103 page 18 of 86 slg46170 7.4 i/o register settings 7.4.1 pin 2 regi ster settings table 11. pin 2 register settings signal function register bit address register definition pin 2 mode control <845:844> 00: digital input without schmitt tr igger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved pin 2 pull down resistor value selection <847:846> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor
000-0046170-103 page 19 of 86 slg46170 7.4.2 pin 3 regi ster settings 7.4.3 pin 4 regi ster settings table 12. pin 3 register settings signal function register bit address register definition pin 3 mode control <857:855> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 3 pull up/down resistor value selection <859:858> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 3 pull up/down resistor selection <860> 0: pull down resistor 1: pull up resistor pin 3 driver strength selection <861> 0: 1x 1: 2x table 13. pin 4 register settings signal function register bit address register definition pin 4 mode control <864:862> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 4 pull up/down resistor value selection <866:865> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 4 pull up/down resistor selection <867> 0: pull down resistor 1: pull up resistor pin 4 driver strength selection <868> 0: 1x 1: 2x
000-0046170-103 page 20 of 86 slg46170 7.4.4 pin 5 regi ster settings 7.4.5 pin 6 regi ster settings table 14. pin 5 register settings signal function register bit address register definition pin 5 mode control <871:869> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 5 pull up/down resistor value selection <873:872> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 5 pull up/down resistor selection <874> 0: pull down resistor 1: pull up resistor pin 5 driver strength selection <875> 0: 1x 1: 2x table 15. pin 6 register settings signal function register bit address register definition pin 6 mode control <878:876> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 6 pull up/down resistor value selection <880:879> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 6 pull up/down resistor selection <881> 0: pull down resistor 1: pull up resistor pin 6 driver strength selection <882> 0: 1x 1: 2x
000-0046170-103 page 21 of 86 slg46170 7.4.6 pin 7 regi ster settings table 16. pin 7 register settings signal function register bit address register definition pin 7 mode control <892:890> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 7 pull up/down resistor value selection <894:893> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 7 pull up/down resistor selection <895> 0: pull down resistor 1: pull up resistor pin 7 driver strength selection <896> 0: 1x 1: 2x
000-0046170-103 page 22 of 86 slg46170 7.4.7 pin 8 regi ster settings 7.4.8 pin 10 register settings table 17. pin 8 register settings signal function register bit address register definition pin 8 mode control <899:897> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 8 pull up/down resistor value selection <901:900> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 8 pull up/down resistor selection <902> 0: pull down resistor 1: pull up resistor pin 8 driver strength selection <903> 0: 1x 1: 2x pin 8 4x drive (4x, nmos open drain) selection <904> 0: 4x drive off 1: 4x drive on (if <897:899> = 101) table 18. pin 10 register settings signal function register bit address register definition pin 10 mode control <936:934> 000: digital inpu t without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 10 pull up/down resistor value selection <938:937> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 10 pull up/down resistor selection <939> 0: pull down resistor 1: pull up resistor pin 10 driver strength selection <940> 0: 1x 1: 2x
000-0046170-103 page 23 of 86 slg46170 7.4.9 pin 11 register settings 7.4.10 pin 12 register settings table 19. pin 11 register settings signal function register bit address register definition pin 11 mode control <943:941> 000: digital inpu t without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 11 pull up/down resistor value selection <945:944> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 11 pull up/down resistor selection <946> 0: pull down resistor 1: pull up resistor pin 11 driver strength selection <947> 0: 1x 1: 2x table 20. pin 12 register settings signal function register bit address register definition pin 12 mode control <950:948> 000: digital inpu t without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 12 pull up/down resistor value selection <952:951> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 12 pull up/down resistor selection <953> 0: pull down resistor 1: pull up resistor pin 12 driver strength selection <954> 0: 1x 1: 2x
000-0046170-103 page 24 of 86 slg46170 7.4.11 pin 13 register settings 7.4.12 pin 14 register settings table 21. pin 13 register settings signal function register bit address register definition pin 13 mode control <957:955> 000: digital inpu t without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 13 pull up/down resistor value selection <959:958> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 13 pull up/down resistor selection <960> 0: pull down resistor 1: pull up resistor pin 13 driver strength selection <961> 0: 1x 1: 2x table 22. pin 14 register settings signal function register bit address register definition pin 14 mode control <964:962> 000: digital inpu t without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved pin 14 pull up/down resistor value selection <966:965> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 14 pull up/down resistor selection <967> 0: pull down resistor 1: pull up resistor pin 14 driver strength selection <968> 0: 1x 1: 2x
000-0046170-103 page 25 of 86 slg46170 7.5 gpi io structure 7.5.1 gpi io structure (for pin 2) figure 2. pin 2 gpi io structure diagram pad digital in s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schmitt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: reserved
000-0046170-103 page 26 of 86 slg46170 7.6 register oe io structure 7.6.1 register oe io structure (for pins 3, 4, 5, 6, 7, 10, 1 1, 12, 13, 14) figure 3. register oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: reserved 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: reserved digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en 2x_en odp_en
000-0046170-103 page 27 of 86 slg46170 7.7 register oe io st ructure with 4x drive 7.7.1 register oe io structu re with 4x drive (for pin 8) figure 4. register oe io with 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1 001: digital in with schmitt trigger, smt_en=1 010: low voltage digital in mode, lv_en = 1 011: reserved 100: push-pull mode, pp_en=1 101: nmos open drain mode, odn_en=1 110: pmos open drain mode, odp_en=1 111: reserved digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en 2x_en odp_en digital out oe odn_en 4x_en
000-0046170-103 page 28 of 86 slg46170 8.0 connection matrix the connection matrix in the sl g46170 is used to create the int ernal routing for internal functions of the device once it is programmed. the registers are pr ogrammed from the one-time nvm cell during test mode operation. all of the connection point for each logic cell within the slg46170 has a specific digital bit code assigned to it that is either set to active high or inactive low based on the design that is created. once the 1024 regist er bits within the slg46170 are programmed a fully custom circu it will be created. the connection matrix has 64 inpu ts and 95 outputs. each of the 64 inputs to the connection matrix is hard-wired to a particul ar source macrocell, including i/o pins, luts, other digital resou rces and v dd and gnd. the input to a digital macrocell uses a 6-bit register to select one o f these 64 input lines. . figure 5. connection matrix gnd 0 pin 2 digital in 1 pin 3 digital in 3 pin 4 digital in 4 matrix input signal functions n nrst_core (por) 62 vdd 63 n function registers 93 input of filter_1 reg<563:558> 0 pin4 digital output source reg<23:18> 1 pin4 digital output source reg<29:24> 2 pin5 digital output source reg<35:30> matrix inputs matrix outputs
000-0046170-103 page 29 of 86 slg46170 8.1 matrix input table table 23. matrix input table n matrix input signal function matrix decode 5 4 3 2 1 0 0 gnd 000000 1 pin2 digital input 0 0 0 0 0 1 2 reserved 000010 3 pin3 digital input 0 0 0 0 1 1 4 pin4 digital input 0 0 0 1 0 0 5 pin5 digital input 0 0 0 1 0 1 6 pin6 digital input 0 0 0 1 1 0 7 reserved 000111 8 pin7 digital input 0 0 1 0 0 0 9 pin8 digital input 0 0 1 0 0 1 10 counter/delay_0 output 14 bit 0 0 1 0 1 0 11 counter/delay_1 output 14 bit w/ ext ck and reset 0 0 1 0 1 1 12 counter/delay_2 output 8 b it w/ ext ck and reset 0 0 1 1 0 0 13 counter/delay_3 output 8 b it w/ ext ck and reset 0 0 1 1 0 1 14 counter/delay_4 output 8 bit 0 0 1 1 1 0 15 counter/delay_5 output 8 bit 0 0 1 1 1 1 16 counter/delay_6 output 8 bit 0 1 0 0 0 0 17 counter/delay _7 output 14 bit 0 1 0 0 0 1 18 dff/latch_0 q output w ith nrst or nset 0 1 0 0 1 0 19 dff/latch_0 nq output with nrst or nset 0 1 0 0 1 1 20 dff/latch_1 output wit h nrst or nset 0 1 0 1 0 0 21 dff/latch_2 output wit h nrst or nset 0 1 0 1 0 1 22 dff/latch_3 output wit h nrst or nset 0 1 0 1 1 0 23 dff/latch_5 output 0 1 0 1 1 1 24 dff/latch_6 output 0 1 1 0 0 0 25 lut4_0 output 0 1 1 0 0 1 26 lut3_0 output 0 1 1 0 1 0 27 lut3_1 output 0 1 1 0 1 1 28 lut3_2 output 0 1 1 1 0 0 29 lut3_3 output 0 1 1 1 0 1 30 lut3_4 output 0 1 1 1 1 0 31 lut3_5 output 0 1 1 1 1 1 32 lut3_6 output 1 0 0 0 0 0 33 lut3_7 output 1 0 0 0 0 1 34 lut3_8 output (1st stage pipe 1 delay output) 1 0 0 0 1 0 35 lut3_9 output 1 0 0 0 1 1
000-0046170-103 page 30 of 86 slg46170 36 lut2_0 output (dff/ latch_4 output) 1 0 0 1 0 0 37 lut2_1 output 1 0 0 1 0 1 38 lut2_2 output 1 0 0 1 1 0 39 lut2_3 output 1 0 0 1 1 1 40 lut2_4 output 1 0 1 0 0 0 41 lut2_5 output 1 0 1 0 0 1 42 pipe1 delay output0 1 0 1 0 1 0 43 pipe1 delay output1 1 0 1 0 1 1 44 edge detect output 1 0 1 1 0 0 45 programmable delay with edge detector 1 0 1 1 0 1 46 internal oscillator output 1 0 1 1 1 0 47 internal oscillator divided by 4 output 1 0 1 1 1 1 48 internal oscillator divided by 8, 12, 24, 64 output 1 1 0 0 0 0 49 internal oscillator divided by 3 output 1 1 0 0 0 1 50 reserved 110010 51 reserved 110011 52 reserved 110100 53 reserved 110101 54 pin10 digital input 1 1 0 1 1 0 55 pin11 digital input 1 1 0 1 1 1 56 pin12 digital input 1 1 1 0 0 0 57 pin13 digital input 1 1 1 0 0 1 58 pin14 digital input 1 1 1 0 1 0 59 filter_0 output 1 1 1 0 1 1 60 matrix input<48> divide by 3 1 1 1 1 0 0 61 filter_1 output 1 1 1 1 0 1 62 reset_core (por) a s matrix input 111110 63 vdd 111111 table 23. matrix input table n matrix input signal function matrix decode 5 4 3 2 1 0
000-0046170-103 page 31 of 86 slg46170 8.2 matrix output table table 24. matrix output table register bit address matrix output signal function matrix output number reg<5:0> reserved 0 reg<11:6> matrix out: pin3 digital output source 1 reg<17:12> matrix out: pi n4 digital output source 2 reg<23:18> matrix out: pi n5 digital output source 3 reg<29:24> matrix out: pi n6 digital output source 4 reg<35:30> reserved 5 reg<41:36> matrix out: pi n6 digital output source 6 reg<47:42> matrix out : pin8 digital output source (4x drive) 7 reg<53:48> matrix out: input for d elay0 or counter0 external clo ck 8 reg<59:54> matrix out: input for d elay1 or counter1 reset input 9 reg<65:60> matrix out: input for c ounter1 external clock or dela y1 external clock 10 reg<71:66> matrix out: input for d elay2 or counter2 reset input 1 1 reg<77:72> matrix out: input for c ounter2 external clock or dela y2 external clock 12 reg<83:78> matrix out: input for d elay3 or counter3 reset input 1 3 reg<89:84> matrix out: input for c ounter3 external clock or dela y3 external clock 14 reg<95:90> matrix out: input for d elay4 or counter4 external clo ck 15 reg<101:96> matrix out: input for d elay5 or counter5 external cl ock 16 reg<107:102> matrix out: input for delay6 or counter6 external c lock 17 reg<113:108> matrix out: input for delay7 or counter7 external c lock 18 reg<119:114> matrix out : clock input of dff0 19 reg<125:120> matrix out: data input of dff0 20 reg<131:126> matrix out: nrst (nset) of dff0 21 reg<137:132> matrix out: clock input of dff1 22 reg<143:138> matrix out: data input of dff1 23 reg<149:144> matrix out: nrst (nset) of dff1 24 reg<155:150> matrix out: clock input of dff2 25 reg<161:156> matrix out: data input of dff2 26 reg<167:162> matrix out: nrst (nset) of dff2 27 reg<173:168> matrix out: clock input of dff3 28 reg<179:174> matrix out: data input of dff3 29 reg<185:180> matrix out: nrst (nset) of dff3 30 reg<191:186> matrix out: clock input of dff5 31 reg<197:192> matrix out: data input of dff5 32 reg<203:198> matrix out: clock input of dff6 33 reg<209:204> matrix out: data input of dff6 34 reg<215:210> matrix out: in0 of lut4_0 35 reg<221:216> matrix out: in1 of lut4_0 36
000-0046170-103 page 32 of 86 slg46170 reg<227:222> matrix out: in2 of lut4_0 37 reg<233:228> matrix out: in3 of lut4_0 38 reg<239:234> matrix out: in0 of lut3_0 39 reg<245:240> matrix out: in1 of lut3_0 40 reg<251:246> matrix out: in2 of lut3_0 41 reg<257:252> matrix out: in0 of lut3_1 42 reg<263:258> matrix out: in1 of lut3_1 43 reg<269:264> matrix out: in2 of lut3_1 44 reg<275:270> matrix out: in0 of lut3_2 45 reg<281:276> matrix out: in1 of lut3_2 46 reg<287:282> matrix out: in2 of lut3_2 47 reg<293:288> matrix out: in0 of lut3_3 48 reg<299:294> matrix out: in1 of lut3_3 49 reg<305:300> matrix out: in2 of lut3_3 50 reg<311:306> matrix out: in0 of lut3_4 51 reg<317:312> matrix out: in1 of lut3_4 52 reg<323:318> matrix out: in2 of lut3_4 53 reg<329:324> matrix out: in0 of lut3_5 54 reg<335:330> matrix out: in1 of lut3_5 55 reg<341:336> matrix out: in2 of lut3_5 56 reg<347:342> matrix out: in0 of lut3_6 57 reg<353:348> matrix out: in1 of lut3_6 58 reg<359:354> matrix out: in2 of lut3_6 59 reg<365:360> matrix out: in0 of lut3_7 60 reg<371:366> matrix out: in1 of lut3_7 61 reg<377:372> matrix out: in2 of lut3_7 62 reg<383:378> matrix out: in0 of l ut3_8 or input of pipe delay 63 reg<389:384> matrix out: in1 of l ut3_8 or nrst of pipe delay 64 reg<395:390> matrix out: in2 of l ut3_8 or clock of pipe delay 65 reg<401:396> matrix out: in0 of lut3_9 66 reg<407:402> matrix out: in1 of lut3_9 67 reg<413:408> matrix out: in2 of lut3_9 68 reg<419:414> matrix out: in0 of l ut2_0 or clock input of dff4 69 reg<425:420> matrix out: in1 of l ut2_0 or data input of dff4 70 reg<431:426> matrix out: in0 of lut2_1 71 reg<437:432> matrix out: in1 of lut2_1 72 reg<443:438> matrix out: in0 of lut2_2 73 reg<449:444> matrix out: in1 of lut2_2 74 reg<455:450> matrix out: in0 of lut2_3 75 table 24. matrix output table register bit address matrix output signal function matrix output number
000-0046170-103 page 33 of 86 slg46170 reg<461:456> matrix out: in1 of lut2_3 76 reg<467:462> matrix out: in0 of lut2_4 77 reg<473:468> matrix out: in1 of lut2_4 78 reg<439:474> matrix out: in0 of lut2_5 79 reg<485:480> matrix out: in1 of lut2_5 80 reg<491:486> matrix out: input for programmable delay & edge det ector 81 reg<497:492> matrix out: power down for osc 82 reg<503:498> reserved 83 reg<509:504> reserved 84 reg<515:510> reserved 85 reg<521:516> reserved 86 reg<527:522> matrix out: pin 10 digital output source 87 reg<533:528> matrix out: pin 11 digital output source 88 reg<539:534> matrix out: pin 12 digital output source 89 reg<545:540> matrix out: pin 13 digital output source 90 reg<551:546> matrix out: pin 14 digital output source 91 reg<557:552> matrix out: input of filter_0 92 reg<563:558> matrix out: input of filter_1 93 reg<569:564> reserved 94 table 24. matrix output table register bit address matrix output signal function matrix output number
000-0046170-103 page 34 of 86 slg46170 9.0 combinatorial logic combinatorial logic is supported via fifteen lookup tables (lut s) within the slg46170. there are five 2-bit luts, nine 3-bit l uts, and one 4-bit lut. the device also includes two combination fun ction macrocells that can be us ed as luts. for more details, please see section 10.0 combi nation function macrocells. inputs/outputs for the fifteen luts are configured from the con nection matrix with specific l ogic functions being defined by t he state of nvm bits. the outputs o f the luts can be configured to any user defined function, including the following standard di gital logic devices (and, nand, or, nor, xor, xnor). 9.1 2-bit lut the five 2-bit luts each take in two input signals from the con nection matrix and produce a sing le output, which goes back int o the connection matrix. figure 6. 2-bit luts 2-bit lut1 out in1 in0 reg <579:576> from connection matrix output <71> from connection matrix output <72> to connection matrix input <37> 2-bit lut2 out in1 in0 reg <583:580> from connection matrix output <73> from connection matrix output <74> to connection matrix input <38> 2-bit lut3 out in1 in0 reg <587:584> from connection matrix output <75> from connection matrix output <76> to connection matrix input <39> 2-bit lut4 out in1 in0 reg <591:588> from connection matrix output <77> from connection matrix output <78> to connection matrix input <40> 2-bit lut5 out in1 in0 reg <595:592> from connection matrix output <79> from connection matrix output <80> to connection matrix input <41>
000-0046170-103 page 35 of 86 slg46170 each 2-bit lut uses a 4-bit regi ster signal to define their out put functions; 2-bit lut1 is defined by reg<579:576> 2-bit lut2 is defined by reg<583:580> 2-bit lut3 is defined by reg<587:584> 2-bit lut4 is defined by reg<591:588> 2-bit lut5 is defined by reg<595:592 the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the four 2-bit lut logic cells. table 30. 2-bit lut stand ard digital functions function msb lsb and-2 1000 nand-2 0 1 1 1 or-2 1110 nor-2 0 0 0 1 xor-2 0110 xnor-2 1001 table 25. 2-bit lut1 truth table. in1 in0 out 0 0 reg <576> 0 1 reg <577> 1 0 reg <578> 1 1 reg <579> table 26. 2-bit lut2 truth table. in1 in0 out 0 0 reg <580> 0 1 reg <581> 1 0 reg <582> 1 1 reg <583> table 27. 2-bit lut3 truth table. in1 in0 out 0 0 reg <584> 0 1 reg <585> 1 0 reg <586> 1 1 reg <587> table 28. 2-bit lut4 truth table. in1 in0 out 0 0 reg <588> 0 1 reg <589> 1 0 reg <590> 1 1 reg <591> table 29. 2-bit lut5 truth table. in1 in0 out 0 0 reg <592> 0 1 reg <593> 1 0 reg <594> 1 1 reg <595>
000-0046170-103 page 36 of 86 slg46170 9.2 3-bit lut the nine 3-bit luts each take in three input signals from the c onnection matrix and produce a single output, which goes back into the connecti on matrix. figure 7. 3-bit luts 3-bit lut0 out in1 in0 reg <604:597> from connection matrix output <39> from connection matrix output <40> to connection matrix input <26> 3-bit lut1 out in1 in0 reg <612:605> from connection matrix output <42> from connection matrix output <43> to connection matrix input <27> in2 from connection matrix output <41> in2 from connection matrix output <44> 3-bit lut2 out in1 in0 reg <620:613> from connection matrix output <45> from connection matrix output <46> to connection matrix input <28> 3-bit lut3 out in1 in0 reg <628:621> from connection matrix output <48> from connection matrix output <49> to connection matrix input <29> in2 from connection matrix output <47> in2 from connection matrix output <50> 3-bit lut4 out in1 in0 reg <636:629> from connection matrix output <51> from connection matrix output <52> to connection matrix input <30> 3-bit lut5 out in1 in0 reg <644:637> from connection matrix output <54> from connection matrix output <55> to connection matrix input <31> in2 from connection matrix output <53> in2 from connection matrix output <56> 3-bit lut9 out in1 in0 reg <676:669> from connection matrix output <66> from connection matrix output <67> to connection matrix input<35> in2 from connection matrix output <68> 3-bit lut6 out in1 in0 reg <652:645> from connection matrix output <57> from connection matrix output <58> to connection matrix input <32> 3-bit lut7 out in1 in0 reg <660:653> from connection matrix output <60> from connection matrix output <61> to connection matrix input <33> in2 from connection matrixoutput <59> in2 from connection matrix output <62>
000-0046170-103 page 37 of 86 slg46170 table 31. 3-bit lut0 truth table. in2 in1 in0 out 0 0 0 reg <597> 0 0 1 reg <598> 0 1 0 reg <599> 0 1 1 reg <600> 1 0 0 reg <601> 1 0 1 reg <602> 1 1 0 reg <603> 1 1 1 reg <604> table 32. 3-bit lut1 truth table. in2 in1 in0 out 0 0 0 reg <605> 0 0 1 reg <606> 0 1 0 reg <607> 0 1 1 reg <608> 1 0 0 reg <609> 1 0 1 reg <610> 110 reg <611> 1 1 1 reg <612> table 33. 3-bit lut2 truth table. in2 in1 in0 out 0 0 0 reg <613> 0 0 1 reg <614> 0 1 0 reg <615> 0 1 1 reg <616> 1 0 0 reg <617> 1 0 1 reg <618> 1 1 0 reg <619> 1 1 1 reg <620> table 34. 3-bit lut3 truth table. in2 in1 in0 out 0 0 0 reg <621> 0 0 1 reg <622> 0 1 0 reg <623> 0 1 1 reg <624> 1 0 0 reg <625> 1 0 1 reg <626> 1 1 0 reg <627> 1 1 1 reg <628> table 35. 3-bit lut4 truth table. in2 in1 in0 out 0 0 0 reg <629> 0 0 1 reg <630> 0 1 0 reg <631> 0 1 1 reg <632> 1 0 0 reg <633> 1 0 1 reg <634> 1 1 0 reg <635> 1 1 1 reg <636> table 36. 3-bit lut5 truth table. in2 in1 in0 out 0 0 0 reg <637> 0 0 1 reg <638> 0 1 0 reg <639> 0 1 1 reg <640> 1 0 0 reg <641> 1 0 1 reg <642> 1 1 0 reg <643> 1 1 1 reg <644> table 37. 3-bit lut6 truth table. in2 in1 in0 out 0 0 0 reg <645> 0 0 1 reg <646> 0 1 0 reg <647> 0 1 1 reg <648> 1 0 0 reg <649> 1 0 1 reg <650> 1 1 0 reg <651> 1 1 1 reg <652> table 38. 3-bit lut7 truth table. in2 in1 in0 out 0 0 0 reg <653> 0 0 1 reg <654> 0 1 0 reg <655> 0 1 1 reg <656> 1 0 0 reg <657> 1 0 1 reg <658> 1 1 0 reg <659> 1 1 1 reg <660>
000-0046170-103 page 38 of 86 slg46170 each 3-bit lut uses a 8-bit regi ster signal to define their out put functions; 3-bit lut1 is defined by reg<604:597> 3-bit lut2 is defined by reg<612:605> 3-bit lut3 is defined by reg<620:613> 3-bit lut4 is defined by reg<628:621> 3-bit lut5 is defined by reg<636:629> 3-bit lut6 is defined by reg<644:637> 3-bit lut7 is defined by reg<652:645> 3-bit lut8 is defined by reg<660:653> 3-bit lut9 is defined by reg<676:669> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the six3-bit lut logic cells. table 40. 3-bit lut stand ard digital functions. function msb lsb and-3 10000000 nand-3 01111111 or-3 11111110 nor-3 00000001 xor-3 10010110 xnor-3 01101001 table 39. 3-bit lut9 truth table. in2 in1 in0 out 0 0 0 reg <669> 0 0 1 reg <670> 0 1 0 reg <671> 0 1 1 reg <672> 1 0 0 reg <673> 1 0 1 reg <674> 1 1 0 reg <675> 1 1 1 reg <676>
000-0046170-103 page 39 of 86 slg46170 9.3 4-bit lut the one 4-bit lut takes in four i nput signals fro m the connecti on matrix and produces a single o utput, which goes back into th e connection matrix. the 4-bit lut uses a 16-bit register signal to define the outpu t function; 4-bit lut0 is defined by reg<692:677> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within the 4-bit lut logic cell. figure 8. 2-bit luts table 41. 4-bit lut0 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <677> 0 0 0 1 reg <678> 0 0 1 0 reg <679> 0 0 1 1 reg <680> 0 1 0 0 reg <681> 0 1 0 1 reg <682> 0 1 1 0 reg <683> 0 1 1 1 reg <684> 1 0 0 0 reg <685> 1 0 0 1 reg <686> 1 0 1 0 reg <687> 1 0 1 1 reg <688> 1 1 0 0 reg <689> 1 1 0 1 reg <690> 1 1 1 0 reg <691> 1 1 1 1 reg <692> table 42. 4-bit lut stand ard digital functions. function msb lsb and-4 1000000000000000 nand-40111111111111111 or-4 1111111111111110 nor-4 0000000000000001 xor-4 0110100111001110 xnor-41001011000110001 4-bit lut9 out in1 in0 reg <692:677> from connection matrix output <35> from connection matrix output <36> to connection matrix input <25> in2 from connection matrix output <37> in3 from connection matrix output <38>
000-0046170-103 page 40 of 86 slg46170 10.0 combination function macrocells the slg46170 has two combination function macrocells that can s erve more than one logic or timi ng function. in each case, they can serve as a look up table (lut), or as another logic or timi ng function. see the list below for the functions that can be implemented in these macrocells; ? one macrocell that can serve as either 2-bit lut or as d flip flop ? one macrocell that can serve as either 3-bit lut or as pipe de lay inputs/outputs for the two combination function macrocells are configured from the connection ma trix with specific logic funct ions being defined by the state of nvm bits. when used as a lut to i mplement combinatorial logic fu nctions, the outputs of the luts can be configured to any user def ined function, including the f ollowing standard digital logic devices (and, nand, or, nor, xor, xnor, inverter, buffer and mux for 3-bit and 4-bit luts). 10.1 2-bit lut or d flip flop macrocells there is one macrocell that can serve as either a 2-bit lut or as a d flip flop. when used to implement lut function, the 2- bit lut takes in two input signals from the connection matrix and p roduce a single output, which goes back into the connection matrix. when used to implement d flip flop function, the two input signals from the connection matrix go to the data (d) and clock (clk) inputs for the flip flop, with the output going bac k to the connec tion matrix. 10.1.1 2-bit lut or d flip flop macrocells used as 2-bit luts figure 9. 2-bit lut0 or dff4 dff4 clk d 2-bit lut0 out in0 in1 to connection matrix input <36> 4-bits nvm from connection matrix output <70> 1-bit nvm reg <575:572> reg <596> from connection matrix output <69> q/nq reg <573> output select (q or nq) table 43. 2-bit lut0 truth table. in1 in0 out 0 0 reg <572> 0 1 reg <573> 1 0 reg <574> 1 1 reg <575>
000-0046170-103 page 41 of 86 slg46170 each macrocell, when programmed for a lut function, uses a 4-bi t register to define their output function: 2-bit lut0 is defined by reg<575:572> 10.1.2 2-bit lut or d flip flop macrocells used as d flip flo p register settings 10.2 3-bit lut or pipe delay macrocell there is one macrocell that can serve as either a 3-bit lut or as a pipe delay. when used to implement lut functions, the 3-bit lut takes in th ree input signals from the connection matrix and produces a single output, which goes ba ck into the connection matrix. when used as a pipe delay, there are three inputs signals from the matrix, input (in), clock (clk) and reset (rst). the pipe delay cell is built from 16 d flip-flop logic cells that provid e the three delay options, two of which are user selectable. th e dff cells are tied in series where the output (q) of each delay cel l goes to the next dff cell. the fi rst delay option (one pipe o ut) is fixed at the output of the first flip-f lop stage. the other two outputs (out0 and out1) provi de user selectable options for 1 C 16 stages of delay. there are de lay output points for each set of the out0 and out1 outputs to a 4-input mux that is controlle d by reg <664:661> for out0 and reg <668:665> for out1. the 4-inp ut mux is used to control the se lection of the amount of delay. the overall time of the delay is based on the clock used in the slg46170 design. each dff cell has a time delay of the inverse of the clock time (either extern al clock or the r c oscillator w ithin the slg46722). the sum of the number of dff cells used wi ll be the total time delay of the pipe delay logic cell. table 44. dff4 register settings signal function register bit address register definition lut2_0 or dff4 select 596 0: lut2_0 1: dff4 dff4 or latch select 572 0: dff function 1: latch function dff4 output select 573 0: q output 1: nq output dff4 initial polarity select 574 0: low 1: high
000-0046170-103 page 42 of 86 slg46170 figure 10. 3-bit lut8 or pipe delay 3-bit lut8 out in1 in0 reg <668:661> from connection matrix output <63> from connection matrix output <64> in2 from connection matrix output <65> 16 flip-flops in rst clk from connection matrix output <64> from connection matrix output <63> from connection matrix output <65> reg <668:665> reg <664:661> to connection matrix input <43> to connection matrix input <42> to connection matrix input <34> out1 out0 one pipe out reg <978> 0 1 reg <977> 0 1
000-0046170-103 page 43 of 86 slg46170 10.2.1 3-bit lut or pipe delay macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut8 is defined by reg<668:661> 10.2.2 3-bit lut or pipe del ay macrocells used as pipe delay register settings table 46. pipe delay register settings signal function register bit address register definition lut3_8 or pipe delay output select reg<977> 0: lut3_8 1: 1 pipe delay output out0 select reg<664:661> out1 select reg<668:665> pipe delay out1 polarity select bit reg<978> 0: non-inverted 1: inverted table 45. 3-bit lut8 truth table. in2 in1 in0 out 0 0 0 reg <661> 0 0 1 reg <662> 0 1 0 reg <663> 0 1 1 reg <664> 1 0 0 reg <665> 1 0 1 reg <666> 1 1 0 reg <667> 1 1 1 reg <668>
000-0046170-103 page 44 of 86 slg46170 11.0 digital storage elements (dffs/latches) there are six d flip flop / latches (dff/ latch logic cells with in the slg46170 available for des ign. the source and destinatio n of the inputs and outputs for th e dff/latches are configured fr om the connection matrix. all df f/latch macrocells have user selection for initial state. dff0 has the option to connect bot h the q and q bar outputs to the connection matrix, dff1, dff2, dff3, dff5 and dff6 can only connect the q output to the matrix . the macrocells dff0, dff1, dff2 and dff3 have an additional input from the matrix that can serve as a nset or nr eset function to the macrocell. note that one of the combination function macrocells (lut 2_0 / dff4) can also operate as a dff or a 2-bit lut please see section 10.1 2-bit lut or d flip flop macrocells for the description of this co mbination function macrocell. the operation of the d flip-flop and latch will follow the func tional descriptions below: dff: clk is rising edge triggered , then q = d; otherwise q will not change latch: if clk = 0, then q = d if clk = 1, then q will not change figure 11. dff/latch0 dff/latch0 d reg <693> from connection matrix output <20> to connection matrix input <19> ck from connection matrix output <19> q q to connection matrix input <18> nrstz nsetz 0 1 from connection matrix output <21> 0 1 reg <694> reg <695> initial polarity select dff or latch select
000-0046170-103 page 45 of 86 slg46170 figure 12. dff/latch1 figure 13. dff/latch2 dff/latch1 d reg <696> from connection matrix output <23> ck from connection matrix output <22> q to connection matrix input <20> nrstz nsetz 0 1 from connection matrix output <24> 0 1 reg <698> reg <699> initial polarity select dff or latch select reg <697> output select (q or nq) dff/latch2 d reg <700> from connection matrix output <26> ck from connection matrix output <25> q to connection matrix input <21> nrstz nsetz 0 1 from connection matrix output <27> 0 1 reg <702> reg <703> initial polarity select dff or latch select reg <701> output select (q or nq)
000-0046170-103 page 46 of 86 slg46170 figure 14. dff/latch3 figure 15. dff/latch5 figure 16. dff/latch6 dff/latch3 d reg <709> from connection matrix output <29> ck from connection matrix output <28> q/nq to connection matrix input <22> nrstz nsetz 0 1 from connection matrix output <30> 0 1 reg <706> reg <707> initial polarity select dff or latch select reg <705> output select (q or nq) dff/latch5 d reg <708> from connection matrix output <32> ck from connection matrix output <31> q/nq to connection matrix input <23> reg <710> initial polarity select dff or latch select reg <709> output select (q or nq) dff/latch6 d reg <711> from connection matrix output <34> ck from connection matrix output <33> q/nq to connection matrix input <24> reg <713> initial polarity select dff or latch select reg <712> output select q or nq
000-0046170-103 page 47 of 86 slg46170 11.1 initial polarity operations figure 17. dff polarity operations vdd data clock por nreset (case 1) q with nreset (case 1) nreset (case 2) q with nreset (case 2) initial polarity: high
000-0046170-103 page 48 of 86 slg46170 12.0 counters/delay generators (cnt/dly) there are eight configurable coun ters/delay generators in the s lg46170. two of these counters/ delay generators are 14-bit (cnt/dly 0 and 1), and six of t he counters/delay generators are 8-bit (cnt/dly 2, 3, 4, 5, 6, 7). for flexibility, each of the se macrocells has a large selectio n of internal and external clock sources, as well as the option to chain from the output of the previous (n-1) cnt/dly macroce ll, to implement l onger count / d elay circuits. three of the counter/delay gener ator macrocells (cnt/dly, 1,2,3 ) have two inputs from the connection matrix, one for delay input/reset input (delay_in/reset_in), and one for an external counter/clock source. five of the counter/delay generator macro - cells (cnt/dly 0, 4, 5, 6, 7) have one input from the connectio n matrix, which has a shared function of either a delay input o r an external clock input. figure 18. cnt/dly0 cnt/dly0 counter_end clk to connection matrix input <10> from connection matrix output <8> count_end_out_x-1 reg <714> 0 1 2 3 4 5 6 7 ext. clock rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <731:718> reg <717:715> 0 1 0 1 delay_out delay_in/cnt_ext_clk delay_in cnt clock edge detector
000-0046170-103 page 49 of 86 slg46170 figure 19. cnt/dly1 figure 20. cnt/dly2 cnt/dly1 counter_end clk to connection matrix input <11> from connection matrix output <9> count_end_out_x-1 reg <734> 0 1 2 3 4 5 6 7 ext. clock from cm out <10> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <751:738> reg <737:735> 0 1 0 1 delay_out delay_in reset_in edge detector cnt/dly2 counter_end clk to connection matrix input <12> from connection matrix output <11> count_end_out_x-1 reg <754> 0 1 2 3 4 5 6 7 ext. clock from cm out <12> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <765:758> reg <757:755> 0 1 0 1 delay_out delay_in reset_in edge detector
000-0046170-103 page 50 of 86 slg46170 figure 21. cnt/dly3 figure 22. cnt/dly4 cnt/dly3 counter_end clk to connection matrix input <13> from connection matrix output <13> count_end_out_x-1 reg <768> 0 1 2 3 4 5 6 7 ext. clock from cm out <14> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <779:772> reg <771:769> 0 1 0 1 delay_out delay_in reset_in edge detector cnt/dly4 counter_end clk to connection matrix input <14> from connection matrix output <15> count_end_out_x-1 reg <782> 0 1 2 3 4 5 6 7 ext. clock rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <793:786> reg <785:783> 0 1 0 1 delay_out delay_in/cnt_ext_clk delay_in cnt clock edge detector
000-0046170-103 page 51 of 86 slg46170 figure 23. cnt/dly5 figure 24. cnt/dly6 cnt/dly5 counter_end clk to connection matrix input <15> from connection matrix output <16> count_end_out_x-1 reg <796> 0 1 2 3 4 5 6 7 ext. clock rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <807:800> reg <799:797> 0 1 0 1 delay_out delay_in/cnt_ext_clk delay_in cnt clock edge detector cnt/dly6 counter_end clk to connection matrix input <16> from connection matrix output <17> count_end_out_x-1 reg <810> 0 1 2 3 4 5 6 7 ext. clock rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <821:814> reg <813:811> 0 1 0 1 delay_out delay_in/cnt_ext_clk delay_in cnt clock edge detector
000-0046170-103 page 52 of 86 slg46170 figure 25. cnt/dly7 cnt/dly7 counter_end clk to connection matrix input <17> from connection matrix output <18> count_end_out_x-1 reg <824> 0 1 2 3 4 5 6 7 ext. clock rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <841:828> reg <827:825> 0 1 0 1 delay_out delay_in/cnt_ext_clk delay_in cnt clock edge detector
000-0046170-103 page 53 of 86 slg46170 12.1 cnt/dly timing diagrams figure 26. delay mode timing figure 27. counter mode timing delay_in rc osc: force power on (always running) delay output asynchronous delay variable asynchronous delay variable delay = period x (counter data + 2) + variable variable = 0..1 delay = period x (counter data + 2) + variable variable = 0..1 delay mode (edge select: both, counter data:3) delay_in rc osc: auto power on (powers up from delay in) delay output offset offset delay = offset + period x (counter data + 2) variable = 0..1 offset = approx. 4-22 ? s at room temp. for 2 mhz osc delay = offset + period x (counter data + 2) variable = 0..1 offset = approx. 4-22 ? s at room temp. for 2 mhz osc delay_in clk counter output count start in 2 clk after reset 4 clk period pulse count mode (count data:3), counte r reset (rising edge detect re set by delay_in input)
000-0046170-103 page 54 of 86 slg46170 12.2 cnt/dly0 register settings 12.3 cnt/dly1 register settings 12.4 cnt/dly2 register settings table 47. cnt/dly0 register settings signal function register bit address register definition counter/delay0 mode select reg<714> 0: delay mode 1: counter mode counter/delay0 clock source select (external clock is only for counter mode) reg<717:715> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 7 overflow counter0 control data/delay0 time control reg<731:718> 1-16384: (delay time = (counter control data +2) /f req) delay0 mode select reg<733:732> 0 0: delay on bot h falling and ris ing edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges table 48. cnt/dly1 register settings signal function register bit address register definition counter/delay1 mode select reg<734> 0: delay mode 1: counter mode counter/delay1 clock source select reg<737:735> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 0 overflow counter1 control data/delay1 time control reg<751:738> 1-16384: (delay time = (counter control data +2) /f req) delay1 mode select or asynchronous counter reset reg<753:752> 00: delay on both falling and rising edges (for del ay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode table 49. cnt/dly2 register settings signal function register bit address register definition counter/delay1 mode select reg<754> 0: delay mode 1: counter mode
000-0046170-103 page 55 of 86 slg46170 counter/delay1 clock source select reg<757:755> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 1 overflow counter1 control data/delay1 time control reg<765:758> 1-256: (delay time = (counter control data +2) /fre q) delay1 mode select or asynchronous counter reset reg<767:766> 00: delay on both falling and rising edges (for del ay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode table 49. cnt/dly2 register settings signal function register bit address register definition
000-0046170-103 page 56 of 86 slg46170 12.5 cnt/dly3 register settings 12.6 cnt/dly4 register settings table 50. cnt/dly3 register settings signal function register bit address register definition counter/delay1 mode select reg<768> 0: delay mode 1: counter mode counter/delay1 clock source select reg<771:769> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 2 overflow counter1 control data/delay1 time control reg<779:772> 1-256: (delay time = (counter control data +2) /fre q) delay1 mode select or asynchronous counter reset reg<781:780> 00: delay on both falling and rising edges (for del ay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode table 51. cnt/dly4 register settings signal function register bit address register definition counter/delay4 mode select reg<782> 0: delay mode 1: counter mode counter/delay4 clock source select (external clock is only for counter mode) reg<785:783> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 3 overflow counter4 control data/delay4 time control reg<793:786> 1-256: (delay time = (counter control data +2) /fre q) delay4 mode select reg<795:794> 0 0: delay on bot h falling and ris ing edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges
000-0046170-103 page 57 of 86 slg46170 12.7 cnt/dly5 register settings 12.8 cnt/dly6 register settings table 52. cnt/dly5 register settings signal function register bit address register definition counter/delay5 mode select reg<796> 0: delay mode 1: counter mode counter/delay5 clock source select (external clock is only for counter mode) reg<799:797> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 4 overflow counter5 control data/delay5 time control reg<807:800> 1-256: (delay time = (counter control data +2) /fre q) delay5 mode select reg<809:808> 0 0: delay on bot h falling and ris ing edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges table 53. cnt/dly6 register settings signal function register bit address register definition counter/delay6 mode select reg<810> 0: delay mode 1: counter mode counter/delay6 clock source select (external clock is only for counter mode) reg<813:811> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 5 overflow counter6 control data/delay6 time control reg<821:814> 1-256: (delay time = (counter control data +2) /fre q) delay6 mode select reg<823:822> 0 0: delay on bot h falling and ris ing edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges
000-0046170-103 page 58 of 86 slg46170 12.9 cnt/dly7 register settings table 54. cnt/dly7 register settings signal function register bit address register definition counter/delay67 mode select reg<824> 0: delay mode 1: counter mode counter/delay7 clock source select (external clock is only for counter mode) reg<827:825> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter 6 overflow counter6 control data/delay7 time control reg<841:828> 1-16384: (delay time = (counter control data +2) /f req) delay7 mode select reg<843:842> 0 0: delay on bot h falling and ris ing edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges
000-0046170-103 page 59 of 86 slg46170 13.0 pipe delay (pd) the slg46170 has a pipe delay logic cell that is shared with th e 3-bit lut8 in one of the combination function macrocells. the user can select one of these func tions to use in a design, but not both. please see section 10.2 3-bit lut or pipe delay macrocell for the description of this combination function macrocell.
000-0046170-103 page 60 of 86 slg46170 14.0 programmable delay / edge detector the slg46170 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings (time1) configured in the greenpak designer. the progra mmable time delay cell can generate one of four different delay patterns, rising edge detection , falling edge detection, both e dge detection and both edge delay. these four patterns can be f urther modified with the addition of delayed edge detection, which add s an extra unit of delay as well as glitch rejection during the delay period. see the timing diagrams b elow for further information. note : the input signal must be longer than the delay, otherwise it will be filtered out. 14.1 programmable delay timing diagram - edge detector output figure 28. programmable delay figure 29. edge detector output programmable delay out in reg <1001:1000> from connection matrix output <81> to connection matrix input<45> reg <1003:1002> reg <1004> delayed edge detector output edge mode selection delay value selection time1 edge detector output in rising edge detector falling edge detector both edge detector both edge delay time1 time1 can be set by register
000-0046170-103 page 61 of 86 slg46170 note: for delays and widths refer to table 4. 14.2 programmable delay timing diagram - glitch filtering for edge detector output figure 30. delayed edge detector output figure 31. glitch filtering for edge detector output delayed edge detector output delayed rising edge detector delayed falling edge detector delayed both edge detector delayed both edge delay time2 time2 time1 can be set by register time2 is a fixed value in time1 time1 edge detector output delayed edge detector output in rising edge detector falling edge detector both edge detector both edge delay rising edge detector falling edge detector both edge detector both edge delay
000-0046170-103 page 62 of 86 slg46170 14.3 programmable de lay register settings table 55. programmable de lay register settings signal function register bit address register definition delay value select for programmable delay & edge detector (vdd = 3.3v, typical condition) reg<1001:1000> 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns select the edge mode of programmable delay & edge detector reg<1003:1002> 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay select edge detector output mode reg<1004> 0: edge detector output 1: delayed edge detector output
000-0046170-103 page 63 of 86 slg46170 15.0 additional logic functions the slg46170 has two additional logi c functions that serve as d eglitch filters. 15.1 deglitch filter figure 32. deglitch filter from connection matrix output <92> to connection matrix input <59> from connection matrix output <93> to connection matrix input <61> filter_0 filter_1 reg <1005> reg <1006> c c r r
000-0046170-103 page 64 of 86 slg46170 16.0 rc oscillator (rc osc) 16.1 rc oscillator overview the slg46170 has two internal rc oscillators, one that runs at 25 khz and one that runs at 2 mhz. the user can select one of these fundamental frequencies for the rc osc macrocell, or the fundamental frequency can also c ome from an external clock input (pin 14). there are two divider stages that allow the use r flexibility for introducing clock signals on various connecti on matrix input lines. the first stage divider allows the selection of /1 , /2, /4 or /8 divide down frequency from the fundamental. the second stage divider has an input of one frequency from the first stag e divider, and outputs five different frequencies on connection matrix input lines <45>, <46>, <47>, <48>, and <49>. see figure 33 below for details of the frequencies for each of these five co nnection matrix inputs. if pwr down input of oscillator is low, the oscillator will be turned on. if pwr down input of oscillator is high the oscillat or will be turned off. the pwr down signal has the highest priorit y. the user can select two os c power modes (reg<707>): ?if auto power on <0> is selected, the osc will run when the slg46170 is powered on. ?if force power on <1> is selected, the osc will run only w hen any macrocell that uses osc is powered on. osc can be turned on by: ? register control (force power on) ? delay mode, when delay requires osc ?cnt
000-0046170-103 page 65 of 86 slg46170 16.2 rc osc bl ock diagram figure 33. rc osc block diagram internal rco reg <970> 0: 25 khz 1: 2 mhz / 4 / 8 / 12 / 24 / 64 / 3 / 3 to connection matrix input <46> to connection matrix input <47> to connection matrix input <60> to connection matrix input <49> 0 1 2 3 to connection matrix input <48> reg <976:975> div /1/2/4/8 reg <973:972> first stage divider second stage divider pin 14 ext. clock ext. clk sel reg <974> 0 1 from connection matrix output <82> pwr down
000-0046170-103 page 66 of 86 slg46170 16.3 oscillator power on delay note 1: osc power mode: "auto power on?. note 2: ?osc enable? signal appears when an y macrocell that uses osc is powered on. figure 34. oscillator startup diagram figure 35. rc oscillator maximum po wer on delay vs. vdd at room temperature 0 5 10 15 20 25 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay (s) vdd (v) 25 khz 2 mhz
000-0046170-103 page 67 of 86 slg46170 16.4 oscillator accuracy note: osc power setting: force power on; clock to matrix input - enable; bandgap: turn on by register - enable. note: for more information see section 5.10 osc specifications. figure 36. rc oscillator frequency vs. temperature, rc osc0=2 mh z figure 37. rc oscillator frequency vs. temperature, rc osc0=25 k hz 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v 19 20 21 22 23 24 25 26 27 28 29 -40 -20 0 20 40 60 80 f (khz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v
000-0046170-103 page 68 of 86 slg46170 17.0 power on reset (por) 17.1 por overview the power on reset (por) macrocell will produce a high or 1 s ignal as an output when the device power supply (v dd ) rises to approximately 1.4 v. the typical internal delay for por to r elease por_io will be 1 ms + ? depending on the power slope, because there is adaptive power-up sequence. the next internal signal will be por_core and then por_io_dly, each of which is further delayed by approximately 1 s. the rise of por_io_dl y will trigger the i/o pins to e xit tri-state, and the device w ill become active. 17.2 por timing diagram figure 38. por timing diagram vdd por io por core por_io_dly rst 1.4 v 1 ms + ? 1 ? s 1 ? s output pad determined by function logic tri-state initial state determined by registers s[1:0]
000-0046170-103 page 69 of 86 slg46170 18.0 appendix a - slg46170 register definition register bit address signal function register bit definition reg<5:0> reserved reg<11:6> matrix out pin3 digital output source reg<17:12> matrix out pin4 digital output source reg<23:18> matrix out pin5 digital output source reg<29:24> matrix out pin6 digital output source reg<35:30> reserved reg<41:36> matrix out pin7 digital output source reg<47:42> matrix out pin8 dig ital output source (4x drive) reg<53:48> matrix out input for del ay0 or counter0 external clock reg<59:54> matrix out input for d elay1 or counter1 reset input reg<65:60> matrix out input for counter1 external clock or delay1 external clock reg<71:66> matrix out input for d elay2 or counter2 reset input reg<77:72> matrix out input for counter2 external clock or delay2 external clock reg<83:78> matrix out input for d elay3 or counter3 reset input reg<89:84> matrix out input for counter3 external clock or delay3 external clock reg<95:90> matrix out input for del ay4 or counter4 external clock reg<101:96> matrix out input for delay5 or counter5 external cloc k reg<107:102> matrix out input for d elay6 or counter6 external clo ck reg<113:108> matrix out input for d elay7 or counter7 external clo ck reg<119:114> matrix out clock input of dff0 reg<125:120> matrix out data input of dff0 reg<131:126> matrix out nrst (nset) of dff0 reg<137:132> matrix out clock input of dff1 reg<143:138> matrix out data input of dff1 reg<149:144> matrix out nrst (nset) of dff1 reg<155:150> matrix out clock input of dff2 reg<161:156> matrix out data input of dff2 reg<167:162> matrix out nrst (nset) of dff2 reg<173:168> matrix out clock input of dff3 reg<179:174> matrix out data input of dff3 reg<185:180> matrix out nrst (nset) of dff3 reg<191:186> matrix out clock input of dff5 reg<197:192> matrix out data input of dff5 reg<203:198> matrix out clock input of dff6 reg<209:204> matrix out data input of dff6 reg<215:210> matrix out in0 of lut4_0 reg<221:216> matrix out in1 of lut4_0 reg<227:222> matrix out in2 of lut4_0
000-0046170-103 page 70 of 86 slg46170 reg<233:228> matrix out in3 of lut4_0 reg<239:234> matrix out in0 of lut3_0 reg<245:240> matrix out in1 of lut3_0 reg<251:246> matrix out in2 of lut3_0 reg<257:252> matrix out in0 of lut3_1 reg<263:258> matrix out in1 of lut3_1 reg<269:264> matrix out in2 of lut3_1 reg<275:270> matrix out in0 of lut3_2 reg<281:276> matrix out in1 of lut3_2 reg<287:282> matrix out in2 of lut3_2 reg<293:288> matrix out in0 of lut3_3 reg<299:294> matrix out in1 of lut3_3 reg<305:300> matrix out in2 of lut3_3 reg<311:306> matrix out in0 of lut3_4 reg<317:312> matrix out in1 of lut3_4 reg<323:318> matrix out in2 of lut3_4 reg<329:324> matrix out in0 of lut3_5 reg<335:330> matrix out in1 of lut3_5 reg<341:336> matrix out in2 of lut3_5 reg<347:342> matrix out in0 of lut3_6 reg<353:348> matrix out in1 of lut3_6 reg<359:354> matrix out in2 of lut3_6 reg<365:360> matrix out in0 of lut3_7 reg<371:366> matrix out in1 of lut3_7 reg<377:372> matrix out in2 of lut3_7 reg<383:378> matrix out in0 of l ut3_8 or input of pipe delay reg<389:384> matrix out in1 of l ut3_8 or nrst of pipe delay reg<395:390> matrix out in2 of l ut3_8 or clock of pipe delay reg<401:396> matrix out in0 of lut3_9 reg<407:402> matrix out in1 of lut3_9 reg<413:408> matrix out in2 of lut3_9 reg<419:414> matrix out in0 of l ut2_0 or clock input of dff4 reg<425:420> matrix out in1 of l ut2_0 or data input of dff4 reg<431:426> matrix out in0 of lut2_1 reg<437:432> matrix out in1 of lut2_1 reg<443:438> matrix out in0 of lut2_2 reg<449:444> matrix out in1 of lut2_2 reg<455:450> matrix out in0 of lut2_3 reg<461:456> matrix out in1 of lut2_3 reg<467:462> matrix out in0 of lut2_4 reg<473:468> matrix out in1 of lut2_4 reg<479:474> matrix out in0 of lut2_5 reg<485:480> matrix out in1 of lut2_5 register bit address signal function register bit definition
000-0046170-103 page 71 of 86 slg46170 reg<491:486> matrix out input for programmable delay & edge detec tor reg<497:492> matrix out power down for osc reg<503:498> reserved reg<509:504> reserved reg<515:510> reserved reg<521:516> reserved reg<527:522> matrix out pin10 digital output source reg<533:528> matrix out pin11 digital output source reg<539:534> matrix out pin12 digital output source reg<545:540> matrix out pin13 digital output source reg<551:546> matrix out pin14 digital output source reg<557:552> matrix out input of filter_0 reg<563:558> matrix out input of filter_1 reg<569:564> matrix out reserved reg<571:570> reserved reg<575:572> lut2_0 data or reg<572> dff4 or latch select 0: dff function 1: latch function reg<573> dff4 output select 0: q output 1: nq output reg<574> dff4 initial polarity select 0: low 1: high reg<579:576> lut2_1 data reg<583:580> lut2_2 data reg<587:584> lut2_3 data reg<591:588> lut2_4 data reg<595:592> lut2_5 data reg<596> lut2_0 or dff4 select 0: lut2_0 1: dff4 reg<604:597> lut3_0 data reg<612:605> lut3_1 data reg<620:613> lut3_2 data reg<628:621> lut3_3 data reg<636:629> lut3_4 data reg<644:637> lut3_5 data reg<652:645> lut3_6 data reg<660:653> lut3_7 data reg<668:661> lut3_8 data or pi pe number select reg<664: 661>: out0 select reg<668: 665>: out1 select reg<676:669> lut3_9 data register bit address signal function register bit definition
000-0046170-103 page 72 of 86 slg46170 reg<692:677> lut4_0 data reg<693> dff0 or latch select 0: dff function 1: latch function reg<694> dff0 nrst/nset select 0: nrst from matrix out 1: nset from matrix out reg<695> dff0 initial polarity select 0: low 1: high reg<696> dff1 or latch select 0: dff function 1: latch function reg<697> dff1 output select (q or nq) 0: q output 1: nq output reg<698> dff1 nrst/nset select 1: nset from matrix out 0: nrst from matrix out reg<699> dff1 initial polarity select 0: low 1: high reg<700> dff2 or latch select 0: dff function 1: latch function reg<701> dff2 output select (q or nq) 0: q output 1: nq output reg<702> dff2 nrst/nset select 1: nset from matrix out 0: nrst from matrix out reg<703> dff2 initial polarity select 0: low 1: high reg<704> dff3 or latch select 0: dff function 1: latch function reg<705> dff3 output select (q or nq) 0: q output 1: nq output reg<706> dff3 nrst/nset select 1: nset from matrix out 0: nrst from matrix out reg<707> dff3 initial polarity select 0: low 1: high reg<708> dff5 or latch select 0: dff function 1: latch function reg<709> dff5 output select (q or nq) 0: q output 1: nq output reg<710> dff5 initial polarity select 0: low 1: high reg<711> dff6 or latch select 0: dff function 1: latch function reg<712> dff6 output select (q or nq) 0: q output 1: nq output reg<713> dff6 initial polarity select 0: low 1: high reg<714> counter/delay0 mode select 0: delay mode 1: counter mode register bit address signal function register bit definition
000-0046170-103 page 73 of 86 slg46170 reg<717:715> counter/delay0 clo ck source select (external clock is onl y for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 7 overflow reg<731:718> counter0 control data /delay0 time control 1-16384: ( delay time = (counter control data +2) /freq) reg<733:732> delay0 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<734> counter/delay1 mode select 0: delay mode 1: counter mode reg<737:735> counter/delay 1 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 0 overflow reg<751:738> counter1 control data /delay1 time control 1-16384: ( delay time = (counter control data +2) /freq) reg<753:752> delay1 mode select or asynchronous counter reset 00: delay on both falling and rising edges (for delay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge onl y (for delay & counter reset) 11: no delay on either fa lling or rising edges / high level reset for counter mode reg<754> counter/del ay2 mode selection 0: delay mode 1: counter mode reg<757:755> counter/delay 2 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 1 overflow reg<765:758> counter2 control data /delay2 time control 1-256: (de lay time = (counter co ntrol data +2) /freq) reg<767:766> delay2 mode select or asynchronous counter reset 00: delay on both falling and rising edges (for delay & counter reset) 01: delay on falling edge onl y (for delay & counter re- set) 10: delay on rising edge onl y (for delay & counter re- set) 11: no delay on either falling or rising edges / high level reset for counter mode reg<768> counter/del ay3 mode selection 0: delay mode 1: counter mode register bit address signal function register bit definition
000-0046170-103 page 74 of 86 slg46170 reg<771:769> counter/delay 3 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 2 overflow reg<779:772> counter3 control data /delay3 time control 1-256: (de lay time = (counter co ntrol data +2) /freq) reg<781:780> delay3 mode select or asynchronous counter reset 00: delay on both falling and rising edges (for delay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge onl y (for delay & counter reset) 11: no delay on either fa lling or rising edges / high level reset for counter mode reg<782> counter/delay4 mode selection 0: delay mode 1: counter mode reg<785:783> counter/delay 4 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 3 overflow reg<793:786> counter4 control data /delay4 time control 1-256: (de lay time = (counter co ntrol data +2) /freq) reg<795:794> delay4 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<796> counter/delay5 mode selection 0: delay mode 1: counter mode reg<799:797> counter/delay5 clock source select (external clock is onl y for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 4 overflow reg<807:800> counter5 control data /delay5 time control 1-256: (de lay time = (counter co ntrol data +2) /freq) reg<809:808> delay5 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<810> counter/delay6 mode selection 0: delay mode 1: counter mode register bit address signal function register bit definition
000-0046170-103 page 75 of 86 slg46170 reg<813:811> counter/delay6 clock source select (external clock is onl y for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 5 overflow reg<821:814> counter6 control data /delay6 time control 1-256: (de lay time = (counter co ntrol data +2) /freq) reg<823:822> delay6 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<824> counter/delay7 mode selection 0: delay mode 1: counter mode reg<827:825> counter/delay7 mode selection (external clock is onl y for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock/8 111: counter 6 overflow reg<841:828> counter7 control data /delay7 time control 1-16384:(d elay time = (counter c ontrol data +2)/freq reg<843:842> delay7 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges <845:844> pin2 mode control 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved <847:846> pin2 pull down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <850:848> reserved <852:851> reserved <853> reserved <854> reserved <857:855> pin3 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <859:889> pin3 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m <860> pin3 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable register bit address signal function register bit definition
000-0046170-103 page 76 of 86 slg46170 <861> pin3 driver strength selection 0: 1x 1: 2x <864:862> pin4 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <866:865> pin4 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <867> pin4 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <868> pin4 driver strength selection 0: 1x 1: 2x <871:869> pin5 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <873:872> pin5 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <874> pin5 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <875> pin5 driver strength selection 0: 1x 1: 2x <878:876> pin6 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <880:879> pin6 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <881> pin6 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <882> pin6 driver strength selection 0: 1x 1: 2x <885:883> reserved <887:886> reserved <888> reserved register bit address signal function register bit definition
000-0046170-103 page 77 of 86 slg46170 <889> reserved <892:890> pin7 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <894:893> pin7 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m <895> pin7 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <896> pin7 driver strength selection 0: 1x 1: 2x <899:897> pin8 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <901:900> pin8 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <902> pin8 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <903> pin8 driver strength selection 0: 1x 1: 2x <904> pin8 4x drive (4x, nmo s open drain) selection 0: 4x drive off 1: 4x drive on (if <899: 897> = 101) <907:905> reserved <909:908> reserved <910> reserved <911> reserved <912> reserved <915:913> reserved <917:916> reserved <918> reserved <919> reserved <922:920> reserved <924:923> reserved <925> reserved register bit address signal function register bit definition
000-0046170-103 page 78 of 86 slg46170 <926> reserved <929:927> reserved <931:930> reserved <932> reserved <933> reserved <936:934> pin10 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <938:937> pin10 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <939> pin10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <940> pin10 driver strength selection 0: 1x 1: 2x <943:941> pin11 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <945:944> pin11 pull up/down r esistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <946> pin11 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <947> pin11 driver strength selection 0: 1x 1: 2x <950:948> pin12 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <952:951> pin12 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <953> pin12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable register bit address signal function register bit definition
000-0046170-103 page 79 of 86 slg46170 <954> pin12 driver strength selection 0: 1x 1: 2x <957:955> pin13 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <959:558> pin13 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <960> pin13 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <961> pin13 driver strength selection 0: 1x 1: 2x <964:962> pin14 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved <966:965> pin14 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m <967> pin14 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <968> pin14 driver strength selection 0: 1x 1: 2x reg<969> force rc oscillator on 0: auto power on 1: force power on reg<970> rc oscillator frequency control 0: 25 k 1: 2 m reg<971> reserved reg<973:972> internal oscillator frequency divider control 00: osc/8 01: osc/12 10: osc/24 11: osc/64 reg<974> external clock source select 0: internal oscillator 1: external clock from pin20 reg<976:975> osc clock pre-divider 00: div1 01: div2 10: div4 11: div8 reg<977> lut3_8 or pipe delay output select 0: lut3_8 1: 1 pipe delay output reg<978> pipe delay out1 polarity select bit 0: non-inverted 1: inverted register bit address signal function register bit definition
000-0046170-103 page 80 of 86 slg46170 reg<979> nvm dat a read disable 0: disable (program data can be read) 1: enable (program data cannot be read) reg<980> nvm power down 0: none (or programming enable) 1: power down (or programming disable) reg<981> gpio quick charge enable 0: disable 1: enable reg<983: 982> reserved reg<991:984> reserved reg<999:992> 8-bit pattern id reg<1001:1000> delay value select for pro grammable delay & edge de- tector (vdd 3.3v, typ) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg<1003:1002> select the edge mode of pr ogrammable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg<1004> select edge de tector out put mode 0: edge detector output 1: delayed edge detector output reg<1005> select polar ity of filt er_0 output 0: non-inverted 1: inverted reg<1006> select polar ity of filt er_1 output 0: non-inverted 1: inverted reg<1007> reserved reg<1013:1008 > reserved reg<1014> reserved reg<1015> reserved reg<1023:1016> reserved register bit address signal function register bit definition
000-0046170-103 page 81 of 86 slg46170 19.0 package top marking system definition ppa wwr nn date code + revision part code + assembly site s/n code pin 1 identifier
000-0046170-103 page 82 of 86 slg46170 20.0 package drawing and dimensions stqfn 14l 2 x 2.2mm 0.4p col package jedec mo-220, variation wece
000-0046170-103 page 83 of 86 slg46170 21.0 tape and reel specifications 21.1 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 14l 2x2.2 mm 0.4p col 14 2 x 2.2 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w stqfn 14l 2x2.2 mm 0.4p col 2.2 2.35 0.8 4 4 1.5 1.75 3.5 8 refer to eia-481 specification
000-0046170-103 page 84 of 86 slg46170 22.0 recommended landing pattern 23.0 recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision for reflow prof ile based on package volume of 2.42 mm 3 (nominal). more information can be f ound at www.jedec.org.
000-0046170-103 page 85 of 86 slg46170 24.0 revision history date version change 10/10/2017 1.03 updated electrical spec fixed typos 7/5/2017 1.02 fixed typos updated silego w ebsite & support updated section programmable delay / edge detector updated electrical spec 10/20/2016 1.01 removed references to gpak families 9/28/2016 1.00 prod uction release
000-0046170-103 page 86 of 86 slg46170 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding si lego green products, please vi sit our website. our green product lines feature: greenpak: programmable mixed signal matrix products greenfet1 / greenfet3 / hfet1: mos fet drivers and ultra-small, low rdson load switches greenclk1 / greenclk2 / greenclk 3: crystal replacement technolo gy products are also available for purchase directly from silego a t the silego on line store at http://www.silego.com /buy/ . silego technical support datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and supp ort please send e-mail requests to greenpak@silego.com users of silego products can rec eive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales offices ar e also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted d irectly via e-mail at info@silego.com or user submission form, l ocated at the f ollowing url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed an d qualified for the consumer m arket. applications or uses as critical components in life support devices or systems are n ot authorized. silego technolog y does not assume any liability arising out of such applica- tions or uses of its products. silego technology reserves the r ight to improve product design , functions and reliability without noti


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